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FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 1 september 2012 FDPC8011S powertrench ? power clip 25v asymmetric dual n-channel mosfet features q1: n-channel ? max r ds(on) = 7.3 m at v gs = 4.5 v, i d = 12 a q2: n-channel ? max r ds(on) = 2.1 m at v gs = 4.5 v, i d = 24 a ? low inductance packaging shortens rise/fall times, resulting in lower switching losses ? mosfet integration enables optimum layout for lower circuit inductance and reduced switch node ringing ? rohs compliant general description this device includes two specia lized n-channel mosfets in a dual package. the switch node has been internally connected to enable easy placement and r outing of synchronous buck converters. the control mosfet (q1) and synchronous syncfet tm (q2) have been designed to provide optimal power efficiency. applications ? computing ? communications ? general purpose point of load mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter q1 q2 units v ds drain to source voltage 25 25 v v gs gate to source voltage 12 12 v i d drain current -continuous (package limited) t c = 25 c 20 60 a -continuous t a = 25 c 13 1a 27 1b -pulsed 40 120 e as single pulse avalanche energy (note 3) 21 97 mj p d power dissipation for single operation t a = 25 c 1.6 1a 2.0 1b w power dissipation for single operation t a = 25 c 0.8 1c 0.9 1d t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient 77 1a 63 1b c/w r ja thermal resistance, junction to ambient 151 1c 135 1d r jc thermal resistance, junction to case 5.0 3.5 device marking device package reel size tape width quantity 13od/15od FDPC8011S power clip 33 13 ? 12 mm 3000 units top gnd (lss hsg sw sw sw bottom 3.3 mm x 3.3 mm pin 1 hsg sw sw sw v+ (hsd v+ ls gnd gnd pin 1 v+ lsg gnd gnd pad9 v+(hsd) pad10 gnd(lss) hsg sw sw sw sw v+ lsg gnd gnd
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 2 electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics symbol parameter test conditions type min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v i d = 1 ma, v gs = 0 v q1 q2 25 25 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 10 ma, referenced to 25 c q1 q2 14 24 mv/c i dss zero gate voltage drain current v ds = 20 v, v gs = 0 v v ds = 20 v, v gs = 0 v q1 q2 1 500 a a i gss gate to source leakage current, forward v gs = 12 v/-8 v, v ds = 0 v v gs = 12 v/-8 v, v ds = 0 v q1 q2 100 100 na na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a v gs = v ds , i d = 1 ma q1 q2 0.8 1.1 1.2 1.4 2.2 2.2 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c i d = 10 ma, referenced to 25 c q1 q2 -4 -3 mv/c r ds(on) drain to source on resistance v gs = 10 v, i d = 13 a v gs = 4.5 v, i d = 12 a v gs = 10 v, i d = 13 a,t j =125 c q1 4.6 5.4 5.6 6.0 7.3 7.3 m v gs = 10 v, i d = 27 a v gs = 4.5 v, i d = 24 a v gs = 10 v, i d = 27 a ,t j =125 c q2 1.2 1.4 1.7 1.8 2.1 2.4 g fs forward transconductance v ds = 5 v, i d = 13 a v ds = 5 v, i d = 27 a q1 q2 97 231 s c iss input capacitance q1: v ds = 13 v, v gs = 0 v, f = 1 mhz q2: v ds = 13 v, v gs = 0 v, f = 1 mhz q1 q2 1240 4335 pf c oss output capacitance q1 q2 332 1126 pf c rss reverse transfer capacitance q1 q2 49 143 pf r g gate resistance q1 q2 0.4 0.5 t d(on) turn-on delay time q1: v dd = 13 v, i d = 13 a, r gen = 6 q2: v dd = 13 v, i d = 27 a, r gen = 6 q1 q2 7 13 ns t r rise time q1 q2 2 5 ns t d(off) turn-off delay time q1 q2 20 38 ns t f fall time q1 q2 2 4 ns q g total gate charge v gs = 0 v to 10 v q1 v dd = 13 v, i d = 13 a q2 v dd = 13 v, i d = 27 a q1 q2 19 64 nc q g total gate charge v gs = 0 v to 4.5 v q1 q2 9 30 nc q gs gate to source gate charge q1 q2 2.6 9.3 nc q gd gate to drain ?miller? charge q1 q2 2.3 7.7 nc
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 3 electrical characteristics t j = 25 c unless otherwise noted drain-source diod e characteristics symbol parameter test conditions type min typ max units v sd source to drain diode forward voltage v gs = 0 v, i s = 13 a (note 2) v gs = 0 v, i s = 27 a (note 2) q1 q2 0.8 0.8 1.2 1.2 v t rr reverse recovery time q1 i f = 13 a, di/dt = 100 a/ s q2 i f = 27 a, di/dt = 300 a/ s q1 q2 22 30 ns q rr reverse recovery charge q1 q2 8 32 nc notes: 1.r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2 pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. q1 :e as of 21 mj is based on starting t j = 25 o c; n-ch: l = 1.2 mh, i as = 6 a, v dd = 23 v, v gs = 10 v. 100% test at l= 0.1 mh, i as = 14.5 a. q2: e as of 97 mj is based on starting t j = 25 o c; n-ch: l = 0.6 mh, i as = 18 a, v dd = 23 v, v gs = 10 v. 100% test at l= 0.1 mh, i as = 32.9 a. a. 77 c/w when mounted on a 1 in 2 pad of 2 oz copper c. 151 c/w when mounted on a minimum pad of 2 oz copper b. 63 c/w when mounted on a 1 in 2 pad of 2 oz copper d. 135 c/w when mounted on a minimum pad of 2 oz copper g df ds sf ss g df ds sf ss g df ds sf ss g df ds sf ss
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 4 typical characteristics (q1 n-channel) t j = 25 c unless otherwise noted figure 1. 0.0 0.3 0.6 0.9 1.2 1.5 0 10 20 30 40 v gs = 2.5 v v gs = 3 v v gs = 10 v v gs = 4.5 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max i d , drain current (a) v ds , drain to source voltage (v) on region characteristics f i g u r e 2 . 0 10203040 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v gs = 2.5 v v gs = 4.5 v v gs = 3 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 3.5 v v gs = 10 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 13 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 2345678910 0 4 8 12 16 20 t j = 125 o c i d = 13 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1.01.52.02.53.0 0 10 20 30 40 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.01 0.1 1 10 40 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 5 figure 7. 048121620 0 2 4 6 8 10 i d = 13 a v dd = 15 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 13 v gate charge characteristics figure 8. 0.1 1 10 30 10 100 1000 2000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 50 1 10 50 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. maximum continuous drain cur rent vs. ambient temperature 25 50 75 100 125 150 0 10 20 30 40 50 60 r t jc = 5.0 o c/w v gs = 4.5 v limited by package v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) figure 11. 0.01 0.1 1 10 100 0.01 0.1 1 10 100 100 p s dc 100 ms 10 ms 1 ms 1s i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds ( on ) single pulse t j = max rated r t ja = 151 o c/w t a = 25 o c 10s f o r w a r d b i a s s a f e operating area figure 12. 10 -4 10 -3 10 -2 10 -1 10 0 10 1 100 1000 0.5 1 10 100 1000 single pulse r t ja = 151 o c/w p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics (q1 n-channel) t j = 25 c unless otherwise noted
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 6 figure 13. 10 -4 10 -3 10 -2 10 -1 10 0 10 1 100 1000 0.001 0.01 0.1 1 2 single pulse r t ja = 151 o c/w (note 1b) duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a junction-to- ambient transient thermal response curve typical characteristics (q1 n-channel) t j = 25 c unless otherwise noted
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 7 typical characteristics (q2 n-channel) t j = 25 o c unlenss otherwise noted 0.0 0.2 0.4 0.6 0.8 1.0 0 20 40 60 80 100 120 v gs = 2.5 v v gs = 3 v v gs = 10 v v gs = 4.5 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max i d , drain current (a) v ds , drain to source voltage (v) figure 14. on-region characteristics 0 20406080100120 0 1 2 3 4 5 6 v gs = 2.5 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 3 v v gs = 4.5 v v gs = 10 v figure 15. normalized on-resistance vs drain current and gate voltage figure 16. normalized on-resistance vs junction temperature -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 27 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) 24681 0 0 1 2 3 4 5 6 7 t j = 125 o c i d = 27 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max figure 17. on-resistance vs gate to source voltage figure 18. transfer characteristics 1.0 1.5 2.0 2.5 3.0 0 20 40 60 80 100 120 t j = 125 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 19. source to drain diode forward voltage vs source current 0.0 0.2 0.4 0.6 0.8 1.0 1e-3 0.01 0.1 1 10 100 200 t j = -55 o c t j = 25 o c t j = 125 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v)
typical characteristics (q2 n-channel) t j = 25 o c unlenss otherwise noted figure 20. gate charge characteristics 0 10203040506070 0 2 4 6 8 10 i d = 27 a v dd = 15 v v dd = 10 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 13 v 0.1 1 10 30 50 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss figure 21. capacitance vs drain to source voltage f i g u r e 2 2 . u nc l a m pe d i nd uc t i v e sw itching capability 0.001 0.01 0.1 1 10 100 1000 1 10 100 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche (ms) i as , avalanche current (a) figure 23. maximum continouns
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 9 typical characteristics (q2 n-channel) t j = 25 o c unlenss otherwise noted figure 26. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 10 0 10 1 100 1000 1e-4 1e-3 0.01 0.1 1 2 single pulse r ja = 135 o c/w (note 1b) duty cycle-descending order normalized thermal impedance, z ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 10 syncfet tm schottky body diode characteristics fairchild?s syncfet tm process embeds a schottky diode in parallel with powertrench mosfet . this diode exhibits similar characteristics to a discrete exte rnal schottky diode in parallel with a mosfet. figure 27 shows the reverse recovery characteristic of the FDPC8011S. schottky barrier diodes exhibit significant leakage at high tem- perature and high reverse voltage. this will increase the power in the device. 100 150 200 250 300 350 400 -5 0 5 10 15 20 25 30 35 current (a) time (ns) di/dt = 300 a/ s 0 5 10 15 20 25 10 -6 10 -5 10 -4 10 -3 10 -2 t j = 125 o c t j = 100 o c t j = 25 o c i dss , reverse leakage current (a) v ds , reverse voltage (v) typical char acteristics (continued) figure 27. FDPC8011S syncfet tm body diode reverse recovery characteristic figure 28. syncfet tm body diode reverse leakage versus drain-source voltage
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 11 application information typical application diagram (syn chronous rectifier buck converter) figure 1.power clip in buck converter topology as shown in figure 1, in the power clip package q1 is the hi gh side mosfet (control mosfet) and q2 is the low side mosfet (synchronous mosfet). figure 2 below show s the package pin out. the blue overlay on the drawing indicates a typical pcb land pattern for the part. figure 2.top view of power clip table 1 pin information shows the name and description of each pin. table 1. pin information pin description number name 1 hsg gate signal input of q1 gate 2,3,4 sw switch or phase node, source of q1 and drain of q2 5,6,pad 10 gnd,gnd(lss) pad ground, source of q2 7 lsg gate signal input of q2 gate 8,pad 9 v+, v+(hsd) pad input voltage of sr buck converter, drain of q1
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 12 recommended pcb layout guidelines as a pcb designer, it is necessary to addre ss critical issues in lay out to minimize losses and optimize the performance of the power train. power clip is a high power density solution and all high cu rrent flow paths, such as v+(h sd), sw and gnd(lss) should be short and wide for minimal resistance and induc tance. v+(hsd) and gnd(lss) are the prim ary heat flow paths for the power clip. a recommended layout procedure is discussed below to ma ximize the electrical and thermal performance of the part. figure 3.top/component (green) view and bottom (red) pcb view following is a guideline, not a requirement which the pcb designer should consider. figure 3 shows an example of a well designed layout. the discussion that follows summa rizes the key features of this layout. ? "the input ceramic bypass capacitor between vi n and gnd should be placed as close as po ssible to the pins v+ / v+(hsd) pad and gnd / gnd(lss) pad to help reduce parasitic inductance and high frequency ringing. several capacitors may be placed in parallel, and capacitors may be placed on both the top and bottom si de of the board. the capacitor located immediately adjacen t to the power clip will be the most effective at reducing hf pa rasitic. caps located farther away, or on the opposite side of t he board will also assist, but will be less effe ctive due to increased trace inductance. ? "the power clip package design, with very s hort distance between pins v+ and gnd, al lows for a short connect distance to the input cap. this is a factor that enables the power clip switch loop to have very low parasitic inductance. ? "use large copper areas on the component side to connect the v+ pin and v+ (hsd) pad, and the gnd and gnd(lss) pad. ? "the sw to inductor copper trace is a high current path. it will also be a hi gh noise region due to switching voltage transien ts. the trace should be short and wide to enable a low resistance path and to minimize the size of the noise region. care should be ta ken to minimize coupling of this trace to adjacent traces. the layout in figure 3 shows a good example of this short, wide path. ? "the power trench ? technology mosfets used in the power clip are effect ive at minimizing sw node ringing. they incorporate a proprietary design 1 that minimizes the peak overshoot ring voltage on the switch node (sw). they allow the part to operate well within the breakdown voltage limits. for most layouts, this eliminates the need to add an external snubber circuit. if the de signer chooses to use an rc snubber, it should be placed close to the part between the sw pins and gnd / gnd (lss) pad to dampen the high frequency ringing. ? "the driver ic should be placed relatively cl osed to hsg pin and lsg pin to minimize g drive trace inductance. excessive g tra ce length may slow the switching speed of the hs drive. and it ma y lead to excessive ringing on the ls g. if the designer must p lace the driver a significant distance away from the power clip, it would be a good practice to include a 0 ohm resistor in the ls g path as a place holder. in the final design, if the ls g exhibits excessive lf ringing, efficiency can often be improved by changin g this resistor to a few ohms to dampen the ls g lf ringing. ? "the power clip has very good junction-pcb heat transfer from all power pins. it has much better heat transfer junction-gnd (l ss) than traditional dual fet packages. in most cases, board ground wi ll be the most effective heat transfer path on the pcb. use a large copper area between gnd / gnd(lss)pad pins and board gr ound. to ensure the best ther mal and electrical connection to ground, we recommend using multiple vias to interconnect ground plane layers as shown in figure 3. 1.patent pending
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 13 ? "use multiple vias in parallel on each copper region to interc onnect top, inner and bottom layers. this will reduce resistance and inductance of the vias and will improve t hermal conductivity. vias should be rela tively large, around 8 mils to 10 mils. ? "avoid using narrow thermal reli ef traces on the v+ / v+(hsd) pad and gnd / gnd( lss)pad pins. these will increase hf switch loop inductance. and these will increase ringing of the hf power loop and the sw node.
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 14 dimensional outlin e and pad layout
FDPC8011S powertrench ? power clip ?2012 fairchild semiconductor corporation FDPC8011S rev.c5 www.fairchildsemi.com 15 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions , specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fa irchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform w hen properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably ex pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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* serdes? uhc ? ultra frfet? unifet? vcx? visualmax? voltageplus? xs? ? ? tm datasheet identification product status definition advance information formative / in design datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the ri ght to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specifications. fair child semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specifications on a product t hat is discontinued by fairchild semiconductor. the datasheet is for reference information only. anti-counterfeiting policy fairchild semiconductor corporation?s anti-counterfeiting policy. fairchild?s anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support . counterfeiting of semiconductor parts is a growing problem in th e industry. all manufactures of semiconductor products are expe riencing counterfeiting of their parts. customers who inadvertently purchase counterfeit parts ex perience many problems such as loss of brand reputation, substa ndard performance, failed application, and increased cost of production and manufacturing de lays. fairchild is taking strong measures to protect ourselve s and our customers from the proliferation of counterfeit parts. fairchild strongly encourages cu stomers to purchase fairchild parts either directly from fa irchild or from authorized fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or fr om authorized fairchild distributors are genuine parts, have full traceability, meet fairchild?s quality standards for handing and storage and provide access to fairchild?s full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and wi ll appropriately address and warranty issues that may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from unau thorized sources. fairchild is committed to combat this global problem and encourage our custom ers to do their part in stopping this practice by buying direct or from authorized distributors. rev. i61 ?

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